1. Field of the Invention
The present invention relates to a memory apparatus for supporting a multi-processor function, and more particularly, to a memory apparatus which overcomes the problems such as an increase in the area of a system board and a signal delay by constructing an instruction memory storing the instruction information required for system operation and a data memory storing data (hereinafter, ‘execution data’) required for the execution of an instruction in a single memory chip.
2. Description of the Background Art
With the complexity of systems and the improvement of their functions and performances, central processing units (hereinafter, ‘CPU’) having multi-data ports have appeared.
In order to realize a memory required for the specification of such a CPU, a data port structure being adaptable well to the structure of the CPU is needed.
Conventional memory apparatuses have restricted characteristics for each individual memory type. Thus, to construct a system by matching a CPU having multi-data ports with a memory, after a plurality of memory apparatuses having different characteristics are provided separately, each of the memory apparatuses should be connected in accordance with multi-data ports of the CPU.
FIG. 1 is a system configuration view briefly showing the structure of a system using two memory apparatuses having different characteristics in the conventional art.
The system of FIG. 1 includes a CPU having multi-ports, an instruction memory storing instruction information and a data memory storing execution data.
At this time, the instruction memory and the data memory are separately constructed. And, they are connected to the CPU via an instruction bus and a data bus respectively.
However, as shown in FIG. 1, when the system is provided with memories having different characteristics, the area of a system board is increased and a delay margin on the data bus is reduced, thereby degrading the performance of the system.